VERICOMP
The strategic project VERICOMP successfully addressed the central challenge of modern embedded systems: creating architectures that are both highly flexible and formally verifiable. In an era where systems must adapt to changing requirements at runtime, traditional static hardware designs are no longer sufficient. VERICOMP pioneered an innovative solution by developing a RISC-V-based microcontroller architecture that leverages Dynamic Partial Reconfiguration (DPR). This allows the system to swap specialized hardware accelerators on the FPGA at runtime, tailoring the hardware to the immediate needs of the application without interrupting the core processes. This breakthrough was achieved through a close and effective collaboration between Pro²Future and the Institute of Technical Informatics at the TU Graz.
A key achievement of the project was the development of a seamless software-fallback mechanism. If a required hardware accelerator is not currently loaded, the system does not fail. Instead, it automatically switches to a software emulation of the function while simultaneously triggering the DPR process in the background. Once the hardware is reconfigured, the system transitions smoothly and transparently back to the significantly faster hardware execution. This ensures both high availability and optimal performance. The entire concept was built upon the HADES-V framework, an open educational platform for RISC-V processor design, which provided a robust and modular foundation. The successful implementation and evaluation of this complex hardware-software co-design demonstrates a significant step towards the next generation of adaptive, reliable and high-performance embedded systems.
Goals
The primary goal of VERICOMP was to investigate and develop methods for the design of reconfigurable processor architectures combined with robust verification techniques for embedded software. The project aimed to create a system that could dynamically adapt its hardware capabilities to meet the real-time demands of an application, thereby optimizing resource utilization, performance, and energy efficiency.
A central objective was the implementation of a RISC-V microcontroller on an FPGA that supports Dynamic Partial Reconfiguration (DPR) to exchange hardware accelerators during operation. This included the development of a standardized, core-independent interface for dynamic instruction set extensions. Furthermore, the project sought to ensure system reliability through a novel software-fallback mechanism, which guarantees functionality even when a specific hardware accelerator is temporarily unavailable. The ultimate goal was to demonstrate the feasibility and benefits of this approach in a tangible prototype, proving that flexibility and formal correctness are not mutually exclusive in the design of embedded real-time systems.
Approach
The project's approach was systematic and built upon a solid foundation. As a starting point, the HADES-V educational framework was used, which provided a modular and well-understood 5-stage RISC-V processor core. This core was then extended to include two Reconfigurable Partitions (RPs), which serve as slots for the hardware accelerators. To manage the communication between the processor and these dynamic extensions, the SCAIE-V interface was employed. This standardized interface allowed for the clean integration of custom instructions that control the hardware accelerators. The core of the innovation was the development of a custom hardware module that automatically triggers a DPR process and manages seamlessly switching to a software-emulated fallback if a requested accelerator is not present.
Expected and Achieved Results
The VERICOMP project successfully achieved all its ambitious goals and delivered a set of outstanding results that demonstrate the power of reconfigurable hardware. The primary outcome is a fully functional and extensively evaluated RISC-V microcontroller that masterfully combines high performance with unprecedented flexibility.
A key achievement is the implementation of the Dynamic Partial Reconfiguration (DPR) capability, which allows the system to load and unload specialized hardware accelerators at runtime. This was successfully demonstrated with several application examples, including Gray-Code conversion, Zero-Overhead-Loops, and the computationally intensive ASCON encryption algorithm. The evaluation clearly showed that the hardware accelerators provide a massive performance boost compared to pure software implementations.
Equally important was the successful development of the seamless software-fallback mechanism. The system robustly handles situations where a required accelerator is not present by switching to a software emulation and automatically loading the necessary hardware in the background. The subsequent transparent handover to the much faster hardware accelerator was flawlessly demonstrated. This ensures that the system remains fully operational at all times, combining reliability with performance.
The project also produced a comprehensive Master's Thesis that documents the entire hardware and software co-design in detail, as well as several scientific publications for high-ranking international conferences (e.g., DSD'25), ensuring the dissemination of the results within the scientific community.
